1. Field of the Invention
The present invention relates to a sense amplifier and, more particularly, to a sense amplifier used in an EP-ROM (Erasable Programmable ROM) and a logic MOS IC incorporating an EP-ROM.
2. Description of the Related Art
FIG. 1 shows a conventional sense amplifier using an EP-ROM as a signal source to be detected. Referring to FIG. 1, the source of EP-ROM 1 as the signal source to be detected is grounded, and its drain is connected to the source of n-channel MOS transistor 2 (to be simply referred to as an NMOS transistor hereinafter). The drain of NMOS transistor 2 is connected to the drain of p-channel MOS transistor 3 (to be simply referred to as a PMOS transistor hereinafter) and the input terminal of CMOS two-stage inverter 4. Power source S is connected to the source of PMOS transistor 3, whose gate is grounded. Voltage Via is applied to the gate of NMOS transistor 2 so as to turn on NMOS transistor 2. Note that the ON resistance of PMOS transistor 3 is set to be sufficiently larger than the sum of the ON resistances of EP-ROM 1 and NMOS transistor 2.
An operation principle of the conventional sense amplifier will be described below.
When EP-ROM 1 is ON, both NMOS transistor 2 and PMOS transistor 3 are rendered conductive. As a result, current flows from power source S to ground E through PMOS transistor 3, NMOS transistor 2, and EP-ROM 1. When the current flows in this manner, since the ON resistance of PMOS transistor 3 is set to be sufficiently larger than the sum of the ON resistances of EP-ROM 1 and NMOS transistor 2, a great voltage drop occurs across PMOS transistor 3, and the potential at drain (point A) of PMOS transistor 3 becomes substantially 0 V. Since the potential at point A becomes close to 0 V, output OUT is set to 0 V through two-stage inverter 4.
On the other hand, when EP-ROM 1 is OFF, NMOS transistor 2 is rendered nonconductive, and PMOS transistor 3 is rendered conductive. As a result, the potential at point A is pulled up to power source voltage V.sub.DD by PMOS transistor 3. When the potential at point A is set to power source voltage V.sub.DD, output OUT is set to power source voltage V.sub.DD through inverter 4.
Note that NMOS transistor 2 is a transistor for voltage control, and is used to prevent a high voltage from being applied to be sense amplifier when data is written in an EP-ROM cell.
A drawback of the above-described prior art is that the operation speed of the sense amplifier is low. That is, a considerably long period of time is required to cause the potential at the darin (point A) of PMOS transistor 3 to rise from 0 V to V.sub.DD when EP-ROM 1 is turned off. This is because charging speeds of circuit capacitances such as a wiring capacitance and capacitances of the diffusion layers of NMOS and PMOS transistors 2 and 3 are slow. The charging speeds are slow because the ON resistance of PMOS transistor 3 is large. In order to increase the charging speeds, the ON resistance of PMOS transistor 3 may be decreased. If, however, the ON resistance of PMOS transistor 3 is set to be smaller than the sum of ON resistances of EP-ROM 1 and NMOS transistor 2, a voltage drop across PMOS transistor 3 is small and the potential at point A becomes higher than V.sub.DD /2 when EP-ROM 1 is turned on. It is very difficult to set the threshold of the first-stage inverter of two-stage inverter 4 to a value between potential V.sub.DD /2 and power source voltage V.sub.DD because of variations in actual transistor characteristics. Therefore, the ON resistance of PMOS transistor 3 must be set to be large, resulting in a decrease in operation speed of the sense amplifier.
As described above, the operation speed of the conventional sense amplifier is low, and hence is not suitable for a circuit requiring a high speed operation. For this reason, a circuit employing the conventional sense amplifier cannot be operated in higher frequency regions or cannot process a large amount of data, and has significant drawbacks in terms of cost, reliability, and performance.